Journal article
Yihan Pan, A. Wheeldon, Mohammed Mughal, Shady O. Agwa, T. Prodromakis, A. Serb
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2024
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2024
Semantic Scholar
ArXiv
DBLP
DOI
Cite
Cite
APA
Click to copy
Pan, Y., Wheeldon, A., Mughal, M., Agwa, S. O., Prodromakis, T., & Serb, A. (2024). An Energy-Efficient Capacitive-RRAM Content Addressable Memory. IEEE Transactions on Circuits and Systems Part 1: Regular Papers.
Chicago/Turabian
Click to copy
Pan, Yihan, A. Wheeldon, Mohammed Mughal, Shady O. Agwa, T. Prodromakis, and A. Serb. “An Energy-Efficient Capacitive-RRAM Content Addressable Memory.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers (2024).
MLA
Click to copy
Pan, Yihan, et al. “An Energy-Efficient Capacitive-RRAM Content Addressable Memory.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2024.
BibTeX Click to copy
@article{yihan2024a,
title = {An Energy-Efficient Capacitive-RRAM Content Addressable Memory},
year = {2024},
journal = {IEEE Transactions on Circuits and Systems Part 1: Regular Papers},
author = {Pan, Yihan and Wheeldon, A. and Mughal, Mohammed and Agwa, Shady O. and Prodromakis, T. and Serb, A.}
}
Abstract
Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a $64\times 64$ array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.