APA
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Li, A., Chang, T.-J., Gao, F., Ta, T., Tziantzioulis, G., Ou, Y., … Wentzlaff, D. (2023). CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA. IEEE Solid-State Circuits Letters.
Chicago/Turabian
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Li, Ang, Ting-Jung Chang, Fei Gao, T. Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, et al. “CIFER: A Cache-Coherent 12-Nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable EFPGA.” IEEE Solid-State Circuits Letters (2023).
MLA
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Li, Ang, et al. “CIFER: A Cache-Coherent 12-Nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable EFPGA.” IEEE Solid-State Circuits Letters, 2023.
BibTeX Click to copy
@article{ang2023a,
title = {CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA},
year = {2023},
journal = {IEEE Solid-State Circuits Letters},
author = {Li, Ang and Chang, Ting-Jung and Gao, Fei and Ta, T. and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul J. and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady O. and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, C. and Wentzlaff, D.}
}
This letter presents CIFER, the world’s first open-source, fully cache-coherent, heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip integrates four 64-bit, OS-capable, RISC-V application cores; three TinyCore clusters that each contain six 32-bit, RISC-V compute cores (18 in total); and an electronic design automation-synthesized, standard-cell-based eFPGA. CIFER enables the decomposition of real-world applications and tailored execution (parallelization or specialization) per decomposed task. Our evaluation shows that: 1) the TinyCore clusters increase the throughput and energy efficiency of data- and thread-parallel tasks by up to <inline-formula> <tex-math notation="LaTeX">$7.95\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$7.75\times $ </tex-math></inline-formula> over one 64-bit core, respectively; 2) the eFPGA increases the throughput and energy efficiency of hardware-accelerable tasks by up to <inline-formula> <tex-math notation="LaTeX">$9.29\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$10.62\times $ </tex-math></inline-formula>, respectively; and 3) using coherent caches for data transfer between the processors and the eFPGA increases the throughput and energy efficiency by up to <inline-formula> <tex-math notation="LaTeX">$11.1\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$10.5\times $ </tex-math></inline-formula>, respectively.