Shady Agwa

Research Fellow


Curriculum vitae


[email protected]


+44 (0) 7950676030


School of Engineering

The University of Edinburgh

1.24D Murchison House, King's Buildings Campus, Edinburgh, EH9 3BF, UK



A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation


Journal article


Shady O. Agwa, Eslam Yahya, Y. Ismail
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2018

Semantic Scholar DBLP DOI
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APA   Click to copy
Agwa, S. O., Yahya, E., & Ismail, Y. (2018). A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation. IEEE Transactions on Circuits and Systems Part 1: Regular Papers.


Chicago/Turabian   Click to copy
Agwa, Shady O., Eslam Yahya, and Y. Ismail. “A Low Power Self-Healing Resilient Microarchitecture for PVT Variability Mitigation.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers (2018).


MLA   Click to copy
Agwa, Shady O., et al. “A Low Power Self-Healing Resilient Microarchitecture for PVT Variability Mitigation.” IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2018.


BibTeX   Click to copy

@article{shady2018a,
  title = {A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation},
  year = {2018},
  journal = {IEEE Transactions on Circuits and Systems Part 1: Regular Papers},
  author = {Agwa, Shady O. and Yahya, Eslam and Ismail, Y.}
}

Abstract

Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different error recovery techniques are used to tolerate the process, voltage, and temperature variations. These techniques reduce the throughput by scaling down the frequency or flushing and restarting the errant pipeline. A resilient microarchitecture is introduced in this paper to tolerate the induced delays generated by the voltage scaling and the process, voltage, and temperature variations. This resilient microarchitecture detects and recovers the induced errors without flushing the pipeline and without scaling down the operating frequency. A resilient 16 b $\times16$ b MAC unit was fabricated using Global Foundry 65-nm technology with 18.26% area overhead and upto $1.65\times $ speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency upto 620 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit’s maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 to 1 V saving about 29% of the power consumed by the conventional MAC unit.


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