APA
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Chang, T.-J., Li, A., Gao, F., Ta, T., Tziantzioulis, G., Ou, Y., … Wentzlaff, D. (2023). CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. IEEE Custom Integrated Circuits Conference.
Chicago/Turabian
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Chang, Ting-Jung, Ang Li, Fei Gao, T. Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, et al. “CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.” IEEE Custom Integrated Circuits Conference (2023).
MLA
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Chang, Ting-Jung, et al. “CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.” IEEE Custom Integrated Circuits Conference, 2023.
BibTeX Click to copy
@article{ting-jung2023a,
title = {CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA},
year = {2023},
journal = {IEEE Custom Integrated Circuits Conference},
author = {Chang, Ting-Jung and Li, Ang and Gao, Fei and Ta, T. and Tziantzioulis, Georgios and Ou, Yanghui and Wang, Moyang and Tu, Jinzheng and Xu, Kaifeng and Jackson, Paul J. and Ning, August and Chirkov, Grigory and Orenes-Vera, Marcelo and Agwa, Shady and Yan, Xiaoyu and Tang, Eric and Balkind, Jonathan and Batten, C. and Wentzlaff, D.}
}
Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low core count hinders efficient execution of thread-level-parallel workloads. Second, noncoherent or partially coherent CPU-eFPGA integration inhibits dynamic, random memory sharing. Third, the use of full-custom circuits makes proprietary eFPGAs technology-dependent, inflexible in physical layout, and lacking architectural customizability.